Several circuits for providing level shifting in such situations are known. Most of these known circuits use a double drive, i.e. generally two DMOS (double-diffusion MOS) transistors in opposite phase, which set or reset a bistable circuit which drives an inverter stage to drive the power stage. A schematic example of such a circuit is illustrated in FIG. 1, wherein two DMOS transistors 10 and 12, provided with resistive loads 14 and 16 and with voltage-limiting Zener diodes 18 and 20, drive the set and reset inputs of a flip-flop 22. The output of flip-flop 22 drives a driver 24 for a power stage which is not illustrated.
Since either resistor 14 or resistor 16 carries current in any operating condition, circuits of this type have an undesirable continuous dissipation, besides occupying a large semiconductor area. Circuital variations have been proposed wherein the passive loads are replaced with active loads, in order to avoid continuous dissipation, but at the expense of a greater circuital complexity which further aggravates the problem of area occupation.
Besides double-drive structures, single-drive circuits have been proposed, in which area occupation is reduced but still at the cost of continuous dissipation. An example of this type of circuit is illustrated in FIG. 2, wherein a DMOS transistor 26, with a load constituted by a resistor 28 and by a Zener diode 30 arranged in parallel, drives an inverter driver 32 which drives a power transistor 34. The current pulse generated by the transistor 26 causes switching "on", whereas for switching "off" it is necessary to wait for the increase in the voltage of the drain of the transistor 25, i.e. of the node V1, with respect to the node V2. This voltage increase is controlled by the discharge of the parasitic capacitor 36 between the drain and the source of the transistor 34, and this leads to a delay with respect to double-drive circuits, especially during switching "on". This delay can be decreased by reducing the switching threshold of the following stage or by reducing the load resistor or the parasitic capacitor.
However, the above known circuits have another, subtler, disadvantage, especially for systems in which the supply voltage on the elements which are powered at switching "on", should not have a high slope. In these circuits, an excessively high slope dV/dt of the voltage can produce an injection of current in the parasitic capacitor of the DMOS transistor, which by passing through the load (whether active or passive) creates an unwanted voltage drop which can cause the early switching of the system, i.e. before the arrival of the drive signal on the DMOS transistor. The behavior of the output voltage V on the load as a function of time t is qualitatively illustrated in FIG. 3, where the point A indicates the instant at which the system is switched and the point B indicates the instant at which the drive signal is applied to the DMOS transistor.
Spurious switching "on" of the system could be eliminated by reducing the resistive value of the load, but with the consequence of further increasing dissipation.